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ltc3824 1 3824fg typical a pplica t ion fea t ures a pplica t ions descrip t ion high voltage step-down controller with 40a quiescent current the ltc ? 3824 is a step-down dc/dc controller designed to drive an external p-channel mosfet. with a wide input range of 4v to 60v and a high voltage gate driver, the ltc3824 is suitable for many industrial and automotive high power applications. constant frequency current mode operation provides excellent performance. the ltc3824 can be configured for burst mode operation. burst mode operation enhances low current efficiency (only 40a quiescent current) and extends battery run time. the switching frequency can be programmed up to 600khz and is easily synchronizable. other features include current limit, soft-start, micropower shutdown, and burst mode disable. the ltc3824 is available in a 10-lead mse power package. 5v/2a buck converter n wide input range: 4v to 60v n current mode constant frequency pwm n very low dropout operation: 100% duty cycle n programmable switching frequency: 200khz to 600khz n selectable high effcient burst mode ? operation: 40a quiescent current n easy synchronization n 8v, 2a gate drive (v cc > 10v) for industrial high voltage p-channel mosfet n programmable soft-start n programmable current limit n available in a small 10-pin thermally enhanced mse package n industrial and automotive power supplies n telecom power supplies n distributed power systems l , lt, ltc, ltm and burst mode are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5731964. efficiency and power loss vs load current 3824 ta01 10k 80.6k r s 0.025 51 c cap 0.1f 422k 100pf c out 100f 2 22h v out 5v 2a 0.1f 392k c in 33f 100v 3.3nf ltc3824 sense gate cap v fb v c v cc r set gnd ss sync/mode v in 5.5v to 60v + load current (ma) 60 70 efficiency (%) power loss (w) 90 80 10 100 3824 ta01a 50 100 0.5 1.0 2.0 1.5 0 2.5 efficiency power loss 2000 1000 v in = 12v v in = 40v v in = 40v v in = 12v
ltc3824 2 3824fg p in c on f igura t ion a bsolu t e maxi m u m r a t ings v cc ........................................................................... 65v ss, r set , v fb ............................................................. 4v v c ...............................................................................3v sync/mode ............................................................... 6v v cc C v sense .............................................................. 1v operating junction temperature range (note 2) .................................................. C55c to 150c storage t emperature range ..................... C65 to 150c lead t emperature (soldering, 10 sec) .................. 300c (note 1) 1 2 3 4 5 gnd sync/mode r set v c v fb 10 9 8 7 6 11 cap gate v cc sense ss top view mse package 10-lead plastic msop t jmax = 150c, ja = 43c/w, jc = 3c/w exposed pad (pin 11) is gnd, must be soldered to pcb or d er in f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3824emse#pbf ltc3824emse#trpbf ltbrz 10-lead plastic msop C40c to 125c ltc3824imse#pbf ltc3824imse#trpbf ltcgz 10-lead plastic msop C40c to 125c ltc3824hmse#pbf ltc3824hmse#trpbf ltcgz 10-lead plastic msop C40c to 150c ltc3824mpmse#pbf ltc3824mpmse#trpbf ltcgz 10-lead plastic msop C55c to 150c lead based finish tape and reel part marking* package description temperature range ltc3824emse ltc3824emse#tr ltbrz 10-lead plastic msop C40c to 125c ltc3824imse ltc3824imse#tr ltcgz 10-lead plastic msop C40c to 125c ltc3824hmse ltc3824hmse#tr ltcgz 10-lead plastic msop C40c to 150c ltc3824mpmse ltc3824mpmse#tr ltcgz 10-lead plastic msop C55c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ elec t rical charac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v cc = 12v, r set = 392k, c cap = 0.1f. no load on any outputs, unless otherwise specified. parameter conditions min typ max units supply voltage (v cc ) l 4 60 v supply current (i vcc ) v c 0.4v (switching off), v cc 60v v sync = 0v (burst mode o peration disable) 0.8 1.3 ma supply current (i vcc ) burst mode operation v cc 60v, sync/mode open, v c = 0.6v 40 65 a supply current in shutdown v c 25mv, v cc 60v l 9 20 30 a a v c 25mv, v cc = 12v l 5 10 15 a a voltage amplifier gm reference voltage (v ref ) ltc3824e/ltc3824i ltc3824mp/ltc3824h l l 0.792 0.788 0.788 0.8 0.808 0.812 0.816 v v v transconductance v c = 0.8v, ?i vc = 2a 220 260 370 mho fb input current v fb = v ref (note 3): ltc3824e/ltc3824i l tc3824mp/ltc3824h l l 10 10 30 60 na na v c high i vc = 0 1.6 v
ltc3824 3 3824fg e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3824 is tested under pulsed load conditions such that t j t a . the ltc3824e is guaranteed to meet performance specifcations from 0c to 85c operating junction temperature. specifcations over the C40c to 125c operating junction temperature range are assured by design characterization and correlation with statistical process controls. the ltc3824i is guaranteed over the C40c to 125c operating junction temperature range. the ltc3824h is guaranteed over the C40c to 150c operating junction temperature range. the ltc3824mp is guaranteed the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v cc = 12v, r set = 392k, c cap = 0.1f. no load on any outputs, unless otherwise specified. parameter conditions min typ max units v c low i vc = 0 0.35 0.5 v v c source current v vc = 0.5v to 1.3v, v fb = v ref C100mv (v sync = 0v) 15 a v c sink current v vc = 0.7v to 1.3v, v fb = v ref +100mv (v sync = 0v) 15 a v c threshold for switching off v sync/mode = 0v (note 4) l 0.4 v soft-start current i ss v ss = 0.1v to 1.5v l 3 2.5 5 7.5 8 a a v c burst mode threshold v cc 60v, v c rising, sync/mode open 0.84 v v c burst mode threshold hysteresis v cc 60v 0.04 v sense voltage at burst mode operation (v cc Cv sense ) at 30% duty cycle 70% duty cycle 30 20 mv mv current limit threshold (v cc Cv sense ) v cc 60v: ltc3824e/ltc3824i l tc3824mp/ltc3824h l l 80 75 100 100 120 120 mv mv fb overvoltage threshold v c = 1.6v 8 % sense input current v sense = v cc 0.1 2 a oscillator switching frequency r set = 392k: ltc3824e/ltc3824i l tc3824mp/ltc3824h l l 170 170 200 200 230 240 khz khz r set = 200k l 320 400 460 khz synchronization pulse threshold on sync pin rising edge v sync 1.3 v synchronization frequency range r set = 392k r set = 200k l l 230 460 300 600 khz khz v rset r set = 392k 1.2 v minimum on-time (measured at gate pin) ccm operation (note 5) 350 ns switching frequency foldback v fb = 0.3v l 35 50 75 khz gate driver gate bias voltage (v cc Cv cap ) 9v v cc 60v, i gate = 10ma: ltc3824e/ltc3824i l tc3824mp/ltc3824h l l 7.0 6.8 7.9 7.9 8.8 8.9 v v v cc = 12v, i gate = 15ma l 6.8 v gate bias voltage (v cap Cgnd) 4v v cc 8v, i gate = 10ma 6v v cc 8v, i gate = 15ma l 0.2 0.85 1.5 2.8 v v gate high voltage (v cc Cv gate ) 4v v cc 60v, i gate = C15ma 0.5 0.8 v gate peak source current c gate = 10nf 2.5 a gate low voltage (v gate Cv cap ) 8v v cc 60v, i gate = 15ma 4v v cc < 8v, i gate = 10ma 0.1 0.05 0.5 v v gate peak sink current c gate = 10nf 2.5 a and tested over the full C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifcations is determined by specifc operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ) where ja (in c/w) is the package junction to ambient thermal impedance.
ltc3824 4 3824fg typical p er f or m ance c harac t eris t ics (v cc -v cap ) vs i gate at v drive low i cc vs v cc switching frequency change vs v cc at r set = 392k v ref change vs v cc switching frequency vs r set ? v ref vs temperature t a = 25c unless otherwise noted. i gate (ma) 0 10 v cc -v cap (v) 8.5 8.4 8.3 8.2 8.1 3824 g01 8.0 7.9 7.8 7.7 7.6 20 30 40 50 v cc (v) 0 0 i cc (ma) 1 2 3 10 20 30 40 3824 g02 50 60 v fb = 0.75v v fb = 0.85v v cc (v) 0 ?3 frequency (khz) ?2 ?1 0 1 3 10 20 30 40 3824 g03 50 60 2 v cc (v) 0 ?0.4 v ref (mv) ?0.2 0 0.2 0.4 10 20 30 40 3824 g04 50 60 die temperature (c) ?75 ?50 ?2 ?v ref (mv) ?1 0 1 5 4 3 2 ?25 0 25 50 3824 g06 75 100 150125 note 3: this parameter is tested in a feedback loop that servos v fb to the reference voltage with the v c pin forced to 1v. note 4: this specifcation represents the maximum voltage on v c where switching (gate pin) is guaranteed to be off. the nominal value of v c where switching turns off is 0.7v. note 5: the ltc3824 typically enters burst mode operation when the load is less than one third the current limit. if minimum on-time is violated, cycle skipping may occur at higher current levels. e lec t rical c harac t eris t ics r set (k) 100 100 frequency (khz) 200 300 400 500 700 200 300 3824 g05 400 600
ltc3824 5 3824fg burst mode disabled at i load = 200ma, v out = 5v burst mode operation v out = 3v burst mode operation v out = 5v typical p er f or m ance c harac t eris t ics load current step response v out 10mv/div inductor current 1a/div 4s/div 3824 g07 i load = 200ma v out 50mv/div inductor current 1a/div 20s/div 3824 g08 v in =12v, v out = 3v, i load = 200ma v out 50mv/div inductor current 1a/div 50s/div 3824 g09 v in =12v, v out = 5v, i load = 200ma output voltage ac coupled 100mv/div inductor current 2a/div 100s/div 3824 g10 t a = 25c unless otherwise noted.
ltc3824 6 3824fg pin f unc t ions gnd (pin 1): chip ground pin. sync/mode (pin 2) : synchronization input and burst mode operation enable/disable. if this pin is left open or pulled higher than 2v, burst mode operation will be enabled at light load and the typical threshold of entering burst mode operation is one third of current limit. if this pin is grounded or the synchronization pulse is present with a frequency greater than 20khz then burst mode operation is disabled and the ltc3824 goes into pulse skipping at light loads. to synchronize the ltc3824, the duty cycle of the synchronizing pulse can range from 10% to 70% and the synchronizing frequency has to be higher than the programmed frequency. r set (pin 3): a resistor from r set to ground sets the ltc3824 switching frequency. v c (pin 4): the output of the voltage error amplifier gm and the control signal of the current mode pwm control loop. switching starts at 0.7v, and higher v c corresponds to higher inductor current. when v c is pulled below 25mv, the ltc3824 goes into micropower shutdown. v fb (pin 5): error amplifier inverting input. a resistor divider to this pin sets the output voltage. when v fb is less than 0.5v, the switching frequency will fold back to 50khz to reduce the minimum on-cycle. ss (pin 6): soft-start pin. a capacitor on this pin sets the output ramp-up rate. the typical time for ss to reach the programmed level is (c ? 0.8v)/5 a . sense (pin 7): current sense input pin. a sense re - sistor, r s , from v in to sense sets the current limit to 100mv/r s . v cc (pin 8): chip power supply. power supply bypass- ing is required. gate (pin 9): gate drive for the external p-channel mosfet. typical peak drive current is 2.5a and the drive voltage is clamped to 8v when v cc is higher than 9v. cap (pin 10): a low esr capacitor of at least 0.1f is required from this pin to v cc to bypass the internal regula- tor for biasing the gate driver circuitry. gnd (exposed pad pin 11): ground. must be soldered to pcb with expanded metal trace for rated thermal per - formance.
ltc3824 7 3824fg block d iagra m applica t ions in f or m a t ion operation the ltc3824 is a constant frequency current mode buck controller with programmable switching frequency up to 600khz. referring to the block diagram, the ltc3824s basic functions include a transconductance amplifier gm to regulate the output voltage and control the current mode pwm current loop, the necessary logic to control the pwm switching cycles, a high speed gate driver to drive an external high power p-channel mosfet and a voltage regulator to bias the gate driver circuit. in normal operation each switching cycle starts with switch turn-on and the inductor current is sampled through the current sense resistor. this current is amplified and then compared to the error amplifier output v c to turn the switch off. voltage loop regulates the output voltage to the programmed level through the output resistor divider and the error amplifier. amplifier e1 regulates the gate drive low to approximately 8v below v cc for v cc higher than 9v, and c cap stabilizes the voltage. note that when v cc is lower than 9v, gate drive high will be within 0.5v of v cc and gate drive low within 1v of ground. important features include shutdown, current limit, soft- start, synchronization and low quiescent current. + ? 3824 bd + 50khz foldback sync disable burst mode operation control osc s q 2v 2.5v 1.8v 100k burst mode disable r 0.025v v ref 0.8v 2.5v 5a v c ss shutdown 1.5v gnd 1.1v sync/ mode r set r freq + ? + ? + ? + ? + + ? + + ? + ? + + + ? + ss + c2 c cap 0.1f cap q1 m1 8v b1 0.5v fb rf2 rf1 r s gate y5 l c out v out v in y6 y2 gm r1 2k c1 470pf c ss 0.1f d6 slope comp d7 d4 d1 e1 v cc m2 0.3a y1 or1 sense 0.1v 50pf pwm v ref reference + ? 1 6 + +
ltc3824 8 3824fg applica t ions in f or m a t ion burst mode operation the ltc3824 can be configured for burst mode operation to enhance light load efficiency (only 40a quiescent current) and extend battery run time by leaving the sync/mode pin open or pulling it higher than 2v. in this mode, when output load drops the loop control voltage v c also drops and when v c reaches approximately 0.9v at low duty cycle the ltc3824 goes into sleep mode with the switch turned off. during sleep mode the output voltage drops and v c rises up. when v c goes up to around 70mv the ltc3824 will turn on the switch and the burst cycle repeats. if the sync/mode pin is grounded the burst mode operation will be disabled and the ltc3824 skips cycles at light load. oscillation frequency setting and synchronization the switching frequency of the ltc3824 can be set up to 600khz by a resistor, r freq , from the r set pin to ground. for 200khz, r freq = 392k. see the switching frequency vs r freq graph in the typical performance characteris - tics section. with a 100ns one-shot timer on-chip, the ltc3824 provides flexibility on the sync pulse width. the sync pulse threshold voltage level is about 1.2v. short-circuit protection in normal operation when the output voltage is in regulation, v fb is regulated to 0.8v. if the output is shorted to ground and v fb drops below 0.5v the switching frequency will be reduced to 50khz to allow the inductor current to discharge and prevent current runaway. note that synchronization is enabled only when v fb is above 0.5v. soft-start during soft-start, the voltage on the ss pin (v ss ) is the reference voltage that controls the output voltage and the output ramps up following v ss . the effective range of v ss is from 0v to 0.8v. the typical time for the output to reach the programmed level is: t ss = c ss ? 0.8v 5 a where c ss is the capacitor connected from the ss pin to gnd. overvoltage protection to achieve good output regulation in burst mode operation, an overvoltage comparator, ovp, with a threshold adap - tive to the v c voltage is used to monitor the fb voltage. in burst mode operation with low v c voltage, the ovp threshold is approximately 2% above v ref and the v ref is also shifted lower by 2% to contain the output ripple and to keep output regulation constant. as output load increases, ovp threshold increases with v c voltage to up to 8% above v ref . shutdown mode quiescent current when the v c pin is pulled down below 25mv the ltc3824 goes into micropower shutdown mode and only draws 7a. output voltage programming with a 0.8v feedback reference voltage, v ref , the output voltage, v out , is programmed by a resistor divider as shown in the block diagram. v out = 0.8v (1+r f1 /r f2 ) current sense resistor r s and current limit the maximum current the ltc3824 can deliver is deter - mined by: i out(max) = 100mv/r s C i ripple /2 where 100mv is the internal 100mv threshold across v cc and v sense , and i ripple is the inductor peak-to-peak ripple current. r s should be placed very close to the power switch with very short traces. good kelvin sensing is required for accurate current limit.
ltc3824 9 3824fg applica t ions in f or m a t ion inductor selection the maximum inductor current is determined by : i l(max) = i out(max) + i ripple 2 where i ripple = (v in ? v out ) ? d f ? l and duty cycle d = v out + v d v in + v d v d is the catch diode d1 forward voltage and f is the switching frequency. a small inductance will result in larger ripple current, output ripple voltage and also larger inductor core loss. an empirical starting point for the inductor ripple current is about 40% of maximum dc current. l = (v in? v out ) ? d f ? 0.4 ? i out(max) the saturation current level of the inductor should be sufficiently larger than i l(max) . power mosfet selection important parameters for the power mosfet include the drain-to-source breakdown voltage (bv dss ), the threshold voltage (v gs(th) ), the on-resistance (r ds(on) ) versus gate- to-source voltage, the gate-to-source and gate-to-drain charges (q gs and q gd , respectively), the maximum drain current (i d(max) ) and the mosfets thermal resistance (r th(jc) ) and r th(ja) . the gate drive voltage is set by the 8v internal regulator. consequently, at least 10v v gs rated mosfets are required in high voltage applications. in order to calculate the junction temperature of the power mosfet, the power dissipated by the device must be known. this power dissipation is a function of the duty cycle, the load current and the junction temperature itself (due to the positive temperature coefficient of r ds(on) ) . the power dissipation calculation should be based on the worst-cast specifications for v sense(max) , the required load current at maximum duty cycle, the voltage and temperature ranges, and the r ds(on) of the mosfet listed in the data sheet. the power dissipated by the mosfet when the ltc3824 is in continuous mode is given by : p mosfet = v out + v d v in + v d (i out ) 2 (1 + )r ds(on) + k(v in ) 2 (i out )(c rss )(f) the first term in the equation represents the i 2 r losses in the device and the second term is the switching losses. k (estimated as 1.7) is an empirical factor inversely related to the gate drive current and has the unit of 1/amps. the term accounts for the temperature coefficient of the r ds(on) of the mosfet, which is typically 0.4%/c. c rss is the mosfet reverse transfer capacitance. figure 1 illustrates the variation of normalized r ds(on) over temperature for a typical power mosfet. figure 1. normalized r ds(on) vs temperature from a known power dissipated in the power mosfet, its junction temperature can be obtained using the following formula: t j = t a + p mosfet t3 th(ja) the r th(ja) to be used in this equation normally includes the r th(jc) for the device plus the thermal resistance from the case to the ambient temperature (r th(ca) ). this value of t j can then be compared to the original assumed value used in the calculation. output diode selection the catch diode carries load current during the switch off-time. the average diode current is therefore dependent junction temperature (c) ?50 normalized on-resistance 1.0 1.5 150 3824 f01 0.5 0 0 50 100 2.0
ltc3824 10 3824fg a pplica t ions i n f or m a t ion on the p-channel switch duty cycle. at high input voltages the diode conducts most of the time. as v in approaches v out the diode conducts only a small fraction of the time. the worst condition for the diode is when the output is shorted to ground. under this condition the diode must safely handle the maximum current at close to 100% of the time. therefore, the diode must be carefully chosen to meet the worst case voltage and current requirements. under normal conditions, the average current conducted by the diode is: i d = i out ? (1 C d) a fast switching schottky diode must be used to optimize efficiency. c in and c out selection a low esr input capacitor, c in , sized for the maximum rms p-channel switch current is required to prevent large input voltage transients. the maximum rms capacitor current is given by: i rms = i out(max) v out v in v in v out ? 1 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. the output ripple, ?v out , is determined by: v out i l esr + 1 8fc out ? ? ? ? ? ? the output ripple is highest at maximum input voltage since ?i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long-term reliability. ceramic capaci - tors have excellent low esr characteristics but can have a high voltage coefficient and audible noise. efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power. percentage efficiency can be expressed as: % efficiency = 100%C(l1 + l2 + l3 +......) where l1, l2, l3...are the individual loss components as a percentage of the input power . it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. although all dissipative elements in the circuit produce losses, the following are the main sources: 1. the supply current into v cc . the v cc current is the sum of the dc supply current and the mosfet driver and control currents. the dc supply current into the v cc pin is typically about 1ma. the driver current results from switching the gate capacitance of the power mosfet; this current is typically much larger than the dc current. each time the mosfet is switched on and off, a packet of gate charge q g is transferred from the cap pin to v cc throughout the external bypass capacitor, c cap . the resulting dq/dt is a current that must be supplied to the capacitor by the internal regulator. i q = 1ma + f ? q g p ic = v in ? i q
ltc3824 11 3824fg applica t ions in f or m a t ion 2. power mosfet switching and condution losses: p mosfet = v out + v d v in + v d (i out ) 2 (1 + )r ds(on) + k(v in ) 2 (i out )(c rss )(f) 3. the i 2 r losses of the current sense resistor: p (sense r) = (i out ) 2 ? r ? d where d is the duty cycle 4. the inductor loss due to winding resistance: p (winding) = (i out ) 2 ? r w 5. loss of the catch diode: p (diode) = i out ? v d ? (1Cd) 6. other losses, including c in and c out esr dissipation and inductor core losses, generally account for less than 2% of total losses. pcb layout considerations to achieve best performance from a ltc3824 circuit, the pc board layout must be carefully designed. for lower power applications, a 2-layer pc board is sufficient. however, at higher power levels, a multiple layer pc board is recom - mended. using a solid ground plane under the circuit is the easiest way to ensure that switching noise does not affect the operation. in order to help dissipate the power from the mosfet and diode, keep the ground plane on the layers closest to the layers where power components are mounted. use power planes for the mosfet and diode in order to improve the spreading of heat from these components into the pcb. for best electrical performance the ltc3824 circuit should be laid out as following: place all power components in a tight area. this will minimize the size of high current loops. orient the input and output capacitors and current sense resistor in a way that minimizes the distance between the pads connected to ground plane. place the ltc3824 and associated components tightly together and next to the section with power components. use a local via to ground plane for all pads that connect to ground. use multiple vias for power components. connect the current sense input directly to the current sense resistor pad. v cc and sense are the inputs of the internal current sense amplifier and should be connected as close to the sense resistor pads as possible. a 100pf capacitor is required across the v cc and sense pins for noise filtering and should be placed as close to the pins as possible. design example as an example, the ltc3824 is designed for an automo - tive 5v power supply with the following specifications: maximum i out = 2a, typical v in = 6v to 18v and can reach 60v briefly during load dump condition, and operating switching frequency = 400khz. for f = 400khz, r set is chosen to be 180k. allow inductor ripple current to be 0.8a (40% of the maximum output current) at v in = 18v, l = (18v ? 5v)5v (400khz s 0.8a)18v = 12 h c out will be selected based on the esr that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. for this design a 220f tantalum capacitor is used. for worse-case conditions c in should be rated for at least 1a ripple current (half of the maximum output current). a 47f tantalum capacitor is adequate. a current limit of 3.3a is selected and r sense can be calculated by : r sense = 100mv 3.3a = 0.03 and a 25m resistor can be used.
ltc3824 12 3824fg mse package 10-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1664 rev g) msop (mse) 0910 rev g 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ? 0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 1 2 3 4 5 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8910 10 1 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does not include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 1.68 0.102 (.066 .004) 1.88 0.102 (.074 .004) 0.50 (.0197) bsc 0.305 0.038 (.0120 .0015) typ bottom view of exposed pad option 1.68 (.066) 1.88 (.074) 0.1016 0.0508 (.004 .002) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29 ref t ypical applica t ion 12v 2a buck converter package d escrip t ion 3824 ta02 15k 8.06k 113k 1000pf 68k c out 270f 1f 16v x7r l1 33h v out 12v 2a 0.1f 301k c in1 33f 100v c in2 2.2f 100v 1000pf ltc3824 sense sync/mode gate v fb v c v cc r set gnd ss v in 12.5v to 60v d1 c in1 : sanyo 63mv68ax c in2 : tdk c4532x7r2a225m c out : sanyo oscon, 16sp270m, tdkc2012x7ric105k l1: d104c919as-330m d1: ss3h9 q1: si7465dp q1 + + r s 0.025 100pf c cap 0.1f cap
ltc3824 13 3824fg information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number f 12/10 e-grade ordering information updated to 125c ec header corrected to operation junction temperature updated/corrected note 2 updated block diagram shutdown section updated package updated related parts updated per marketing request 2 2 3 7 8 12 14 g 3/11 updated temperature range for mp-grade part added ltc3824mp to electrical characteristics tables updated note 2 updated typical application 2 2, 3 3 14 (revision history begins at rev f)
ltc3824 14 3824fg linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 0311 rev g ? printed in usa r ela t e d p ar t s typical a pplica t ion 3v 2a buck converter 3824 ta02a 15k 80.6k c cap 0.1f 255k 100pf 51 c out 270f 1f 16v l1 33h v out 3.3v 2a 0.1f 301k c in1 33f 100v c in2 2.2f 100v 1000pf ltc3824 sense sync/mode gate v fb v c v cc r set gnd ss v in 4.5v to 60v d1 q1 + + r s 0.025 100pf c in1 : sanyo 63mv68ax c in2 : tdk c4532x7r2a225m c out : sanyo oscon, 16sp270m, tdkc2012x7ric105k l1: d104c919as-330m d1: ss3h9 q1: si7465dp cap part number description comments ltc3891 60v, low i q synchronous step-down dc/dc controller with 99% duty cycle and low 95ns minimum on-time pll capable fixed operating frequency 50khz to 900khz, 4v v in 60v, 0.8v v out 24v, i q = 50a lt3845a 60v, low i q synchronous step-down dc/dc controller adjustable fixed operating frequency 100khz to 500khz, 4v v in 60v, 1.23v v out 36v, i q = 120a, tssop-16e ltc3812-5 60v synchronous step-down dc/dc controller constant on-time valley current mode, 4v v in 60v, 0.8v v out 0.93v in , tssop-16e ltc3810 100v synchronous step-down dc/dc controller constant on-time valley current mode, 4v v in 60v, 0.8v v out 0.93v in , ssop-28 ltc3890/ltc3890-1 60v, low i q , dual 2-phase synchronous step-down dc/dc controllers with 99% duty cycle and 95ns minimum on-time pll fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v v out 24v, i q = 50a ltc3834/ltc3834-1 ltc3835/ltc3835-1 low i q , single output synchronous step-down dc/dc controllers with 99% duty cycle pll fixed frequency 140khz to 650khz, 4v v in 36v, 0.8v v out 10v, i q = 30a/80a ltc3857/ltc3857-1 ltc3858/ltc3858-1 low i q , dual output 2-phase synchronous step-down dc/dc controllers with 99% duty cycle pll fixed frequency 50khz to 900khz, 4v v in 38v, 0.8v v out 24v, i q = 50a/170a ltc3859 low i q , triple output buck/buck/boost synchronous dc/dc controller all outputs remain in regulation through cold crank, 2.5v v in 38v, v out(buck) up to 24v, v out(boost) up to 60v, i q = 55a

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